Among methods developed to test a system incorporating a component (e.g. a microprocessor), are the use of an "in-circuit emulator" (ICE), and the use of a "clam-shell" tester. Therefore, it is desirable for the component to provide support features to facilitate the use of these testing methods For microprocessor-based system designs, support during system reset and immediately after system reset is particularly important. This is because, during and immediately after reset, the microprocessor has very limited information about the environment and must often be responsible for initializing the environment upon its own reset. In the following discussion, the component under test is referred to as the microprocessor under test. However, it will be appreciated by those skilled in the art that the principles discussed below are applicable to testing of many components including those not commonly known as microprocessors.
Normally, when a reset signal is sent to a microprocessor, a sequence of events is triggered over a period of time known as the "reset period." During the reset period, the control output signals of the microprocessor are typically "negated", i.e. driven to the inactive or non-asserted states by the microprocessor, to allow external state machines and control structures to reset at the same time the microprocessor is being reset.
In an ICE testing environment, however, the reset requirements are different. ICE testing is often performed during design time, when the system is not fully debugged. The ICE provides diagnostic facilities beyond that provided by the microprocessor under test. For example, setting up break points, single-stepping etc. are very commonly provided by an ICE. In order to provide real time testing, the microprocessor under test performs much of its normal functions in the system, but is disabled as to certain functions, which are performed by the ICE under auspices of the ICE's extensive diagnostic facilities. Hence, under ICE testing, the microprocessor under test must remain active during most, if not all, of the testing process. Very often, the ICE includes a copy of the chip under test which is known to be functioning properly. During reset, however, when a microprocessor under test resets from its limited knowledge of the environment, both the microprocessor under test and the ICE will attempt to drive the control signals negated, which may be undesirable under certain situations. It is more desirable that, during the period of reset under such situations, the ICE should be given control of the system and the control output signals of the microprocessor under test should remain tristated, i.e. in a high impedance state. After the reset period, however, it is desirable that the microprocessor under test be allowed to perform normal functions.
Clam-shell testing is often used during manufacturing of a board including the microprocessor (i.e. after system design is fully debugged) to inject test patterns for uncovering manufacturing defects, such as an open circuit or a defective part. In clam-shell testing, especially for a surface-mounted microprocessor, the microprocessor is not removed from the system. Instead, the tester "clamps" onto the microprocessor and completely takes over control of the external circuit from the microprocessor. At all times during clam-shell testing, the output terminals of the microprocessor under test must remain inactive, i.e. all the output terminals must be tristated. Therefore, under the clam-shell testing scheme, the microprocessor must remain tristated during and after the reset period. This requirement is in conflict with that needed for supporting ICE testing, as described above.
In the prior art, a microprocessor such as the R3000 available from Integrated Device Technology, Inc. of Santa Clara, Calif., provides support for tristating the microprocessor output pins after reset to support clam-shell type testing. However, no circuit is known to support both ICE and clam-shell testings in the manner discussed above.